As displays that can be used for large and thin TV sets, plasma display panels (hereinafter abbreviated as PDPs) attract attention. Among the electrode layer, dielectric layer, MgO layer, barrier rib layer and phosphor layer as the components of a PDP, it is known that the electrode layer, dielectric layer, barrier rib layer and phosphor layer can be formed respectively by a method of coating or laminating a base substrate with a photosensitive paste, exposing it through a photo mask having a desired pattern, and developing using a desired developer.
For example, proposed methods are a method comprising the steps of forming a layer consisting of a ceramic powder and a UV-curable resin on a base substrate, exposing it through a photo mask having a desired pattern, and developing to form a barrier rib layer (Patent Document 1), a method comprising the steps of coating a base substrate with a glass paste, drying, coating with a resist, exposing the resist through a photo mask having a desired pattern, developing, and sandblasting to form a barrier rib pattern (Patent Document 2), and a method comprising the steps of coating a barrier rib layer with a photosensitive phosphor paste and exposing it through a photo mask (Patent Document 3).
However, the above methods have a problem that in the case where the photo mask contains foreign matters deposited on it or has flaws, the pattern obtained after exposure and development mostly has defects such as disconnections and short-circuits, to lower the yield.
As a method for solving the problem; it is proposed to prepare a photo mask with the length of its opening kept shorter than the length of the pattern layer and to expose while moving the base substrate or photo mask (Patent Document 4). However, this method has a problem that in the case of a thick pattern of, for example, barrier ribs of a PDP, exposure shortage occurs at the ends in the moving direction of the base substrate or photo mask, to thin or peel the pattern.    [Patent Document 1] JP2-165538A    [Patent Document 2] JP7-320641A    [Patent Document 3] JP2000-113614A    [Patent Document 4] JP2004-240095A